From the EETimes article:

Samsung will describe the first mobile applications processor to use ARM´s big.little concept at ISSCC in February. [...] Samsung will detail a 28-nm SoC with two quad-core clusters. One cluster runs at 1. 8 GHz, has a 2 MByte L2 cache and is geared for high performance apps; the other runs at 1.2 GHz and is tuned for energy efficiency.

Are some of the ISSCC paper committee members leaking?

The big.LITTLE architecture makes a lot of sense, and I’m sure that in the future we’ll see TINY.big.LITTLE.huge architectures.

The ISSCC advance program is online.